Multi-channel peripheral interface using selectively flaggable c

Details Multi-channel peripheral interface using selectively flaggable c Multi-channel peripheral interface using selectively flaggable c

1991-12-18

1993-07-13

Harrell, Robert B.

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3642222, 3642383, 3642419, 3642456, 3642542, 3642473, 36493361, 3649575, 3649671, 364DIG1, 370 32, 395200, 395275, G06F 1310

Patent

active

052281302

ABSTRACT:
Each of the identical register sets associated with each of the multiple channels of a peripheral device includes an initialization register. Setting the appropriate bit in the initialization register of any one of the channels allows the data processing system serviced by the peripheral device to perform a concurrent write operation to the same selected register in each channel enabled for a concurrent write. The concurrent write operation is based on a standard write instruction and a standard system address.

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patent: 4975828 (1990-12-01), Wishneusky et al.
patent: 5063494 (1991-11-01), Davidowski et al.

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