Parallel processor system for detecting the end of data transmis

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39520019, 364DIG1, 364259, 364230, 3642319, 364239, G06F 1516

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active

055112218

ABSTRACT:
In each processing device of a parallel processor system, a processor outputs a signal when all the transmit data are transmitted to a router. A latch receives the signal from the processor to output a signal set to HIGH. To an AND gate are inputted the signal set to HIGH outputted from the latch and a signal set to HIGH which indicates that the router has no receive data received from a network. The parallel processor system performs AND operation on the outputs of the AND gates of all the processing devices, and detects that a data transmit/receive processing is completed among all the processing devices according to the results of AND operation.

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K. Kaneko et al., Processing Element Design for a Parallel Computer, IEEE Micro Magazine, vol. 10, No. 2, pp. 30 et seq., (Apr. 1990).

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