Method for manufacturing vertical PNP transistor with shallow em

Details Method for manufacturing vertical PNP transistor with shallow em Method for manufacturing vertical PNP transistor with shallow em

1983-03-07

1985-08-13

Roy, Upendra

Metal treatment

Compositions

Heat treating

29576B, 148175, 148187, 357 34, 357 91, H01L 21265, H01L 21225

Patent

active

045348065

ABSTRACT:
A PNP semiconductor device and a manufacturing method therefore. In the method, a window is formed on the surface of a semiconductor substrate having an N-type base region formed therein. A polycrystalline layer is formed on the base region in the window. The polycrystalline silicon layer is ion implanted under specific predetermined conditions with a P-type doping ion. The P-type doping ion is diffused by an annealing treatment under predetermined conditions into the base region to form a shallow emitter region.

REFERENCES:
patent: 4029527 (1977-06-01), Glasl et al.
patent: 4063967 (1977-12-01), Graul et al.
patent: 4151006 (1979-04-01), DeGraaff et al.
patent: 4167425 (1979-09-01), Herbst
patent: 4234357 (1980-11-01), Scheppele
patent: 4357622 (1982-11-01), Magdo et al.
patent: 4437897 (1984-03-01), Kemlage
patent: 4452645 (1984-06-01), Chu et al.
Graul et al, IEEE Jour. Solid St. Circuits, SC-11, (1976), p. 491.

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