Test circuit having a plurality of scan latch circuits

Details Test circuit having a plurality of scan latch circuits Test circuit having a plurality of scan latch circuits

1993-01-25

1995-10-10

Voeltz, Emanuel T.

Excavating

371 225, H04B 1700

Patent

active

054576989

ABSTRACT:
A technique for reducing the circuit area of a test circuit which is formed by a parallel register which includes a plurality of scan latch circuits is disclosed. A scan latch circuit is formed by a master-slave latch circuit. The master-slave latch circuit includes a static latch circuit which serves as a master side latch circuit and a dynamic latch circuit which serves as a slave side latch circuit. Under the control of a control signal, either a signal inputted to a first circuit part or a signal inputted to a preceding stage scan latch circuit is held in the static latch circuit. The signal which was inputted to a first circuit part is outputted via an output terminal of the scan latch circuit to a second circuit part. The signal which was inputted to the preceding stage scan latch circuit is advanced to the dynamic latch circuit and thereafter outputted to a next scan latch circuit via other output terminal of the scan latch circuit. Thus, since the dynamic latch circuit is used as the slave since latch circuit, the test circuit includes less elements, thereby less circuit area is required for the test circuit.

REFERENCES:
patent: 3812388 (1974-05-01), Southworth
patent: 4554664 (1985-11-01), Schultz
patent: 4669061 (1987-05-01), Bhavsar
patent: 4760283 (1988-07-01), Weaver
patent: 4910734 (1990-03-01), Segawa et al.
patent: 5012246 (1991-04-01), Chung et al.
patent: 5172011 (1992-12-01), Leuthold et al.
Carver Mead, et al., pp. 66-67, and pp. 75-76, "Introduction to VLSI Systems" Oct. 1980.
Latch Scanning Arrangements, pp. 102-109, Frank F. Tsui, "LSI/VLSI Testability Design" 1987 no month.

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