Boots – shoes – and leggings
Patent
1983-08-12
1986-08-26
Thomas, James D.
Boots, shoes, and leggings
340750, G06F 1206, G09G 114
Patent
active
046086323
ABSTRACT:
In a microcomputer system having a main memory accessed by both the CPU and the CRT controller, a page register system receives page bits defining both CPU and CRT pages from the CPU. The CPU page bits are combined with lower order address bits from the CPU for CPU access cycles, and the CRT page bits are combined with lower order address bits from CRT controller for CRT access cycles. Both the CPU and CRT controller can access any of the pages in the memory. For compatibility with higher level systems, the CPU may provide addresses in a range outside the range of addresses for the memory. When a decoder detects such addresses, it directs CPU address bits, corresponding in order to the CPU page bits, to address the memory instead of the CPU page bits.
REFERENCES:
patent: 4342991 (1982-08-01), Pope et al.
patent: 4346441 (1982-08-01), Plank et al.
patent: 4374410 (1983-02-01), Sakai et al.
patent: 4414622 (1983-11-01), Matsumoto
patent: 4429306 (1984-01-01), Macauley et al.
patent: 4475176 (1984-10-01), Ishii
patent: 4482979 (1984-11-01), May
patent: 4500956 (1985-02-01), Leininger
patent: 4500961 (1985-02-01), Engles
patent: 4503491 (1985-03-01), Lushtak et al.
patent: 4511965 (1985-04-01), Rajaram
International Business Machines - Corporation
Lee Thomas
Thomas James D.
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