Method for fabricating non-volatile memory cells, arrays of non-

Details Method for fabricating non-volatile memory cells, arrays of non- Method for fabricating non-volatile memory cells, arrays of non-

1992-06-03

1993-07-13

Thomas, Tom

Fishing, trapping, and vermin destroying

437 43, 437 48, H01L 2170

Patent

active

052273261

ABSTRACT:
The method is provided for selectively fabricating erasable read-only memory and read-only memory cells at a face of a layer of semiconductor of a first conductivity type. Active areas on the face of the layer of semiconductor are selectively defined by masking the face of the layer of semiconductor and patterning and etching the mask to expose first and second areas of the layer of semiconductor. A layer of conductor is formed insulatively adjacent the active area of each cell being fabricated. The layer of conductor is patterned and etched to define a first level gate conductor adjacent at least a portion of the active area of each cell being fabricated, the first level gate of each read-only memory cell set to a logic zero being fabricated disposed adjacent a one of the insulator regions adjacent a corresponding one of the third exposed areas. A layer of interlevel insulator is formed adjacent the first level gate of each erasable read-only memory cell being fabricated. A second layer of conductor is formed adjacent the layer of interlevel insulator of each erasable memory cell being fabricated. The second layer of conductor, the layer of interlevel insulator, and the first level gate of each erasable read-only memory cell is etched to define a floating gate/control gate stack. Source/drain regions of a second conductivity type opposite the first conductivity type are formed into portions of the active areas of each memory cell being fabricated exposed during the steps of etching.

REFERENCES:
patent: 4358889 (1982-11-01), Dickman et al.
patent: 5057448 (1991-10-01), Kuroda

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