method of manufacturing a new DRAM capacitor structure having in

Details method of manufacturing a new DRAM capacitor structure having in method of manufacturing a new DRAM capacitor structure having in

1994-12-14

1995-10-10

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437191, 437919, H01L 218242

Patent

active

054570654

ABSTRACT:
A method for fabricating a stacked storage capacitor on a dynamic random access memory (DRAM) cell with increased capacitance was accomplished. The stacked capacitor is used with a field effect transistor (FET) as part of a dynamic random access memory (DRAM) cell for storing data in the form of stored charge on the capacitor. The method for making the capacitor involves forming a bottom electrode from a single polysilicon layer having a fin-shaped structure, and then using a second polysilicon layer and a plasma etch back to create a second self-aligned fin-like structure that significantly increases the surface area of the capacitor bottom electrode. The capacitor structure is then completed by forming a thin capacitor dielectric layer on the bottom electrode and depositing a third polysilicon layer to form the top electrode and complete the capacitor with significantly increased capacitance and an economy of processing steps.

REFERENCES:
patent: 5006481 (1991-04-01), Chan et al.
patent: 5059548 (1991-10-01), Kim
patent: 5102820 (1992-04-01), Chiba
patent: 5164337 (1992-11-01), Ogawa et al.
patent: 5223729 (1993-06-01), Kudoh et al.
patent: 5266514 (1993-11-01), Tuan et al.
patent: 5270238 (1993-12-01), Kim
"A newly Designed Planar Stacked Capacitor Cell With High Dielectric Constant Film for 256 Mbit DRAM" by T. Eimori et al, IEEE International Electron Device Meeting Proceedings, Dec. 1993, pp. 631-634.

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