Boots – shoes – and leggings
Patent
1991-10-31
1993-08-31
Shaw, Dale M.
Boots, shoes, and leggings
395275, 364DIG1, 3642711, 3642383, G06F 104, G06F 1300
Patent
active
052416674
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a clock apparatus of an electric equipment such as a video tape recorder which time-controls timer picture recording or the like, and more particularly to a clock apparatus which controls clock information prepared by a sub controller on the basis of the output of a reference oscillator contained in the main controller with high precision in a system in which a main controller and the sub controller are connected through a communication device.
BACKGROUND TECHNOLOGY
Generally, an electric equipment such as a video tape recorder having a timer function includes a micro computer for system controlling (micro computer is written as CPU, hereinafter) which controls the equipment over all and a CPU for a timer, which generates clock information and a timer controlling signal based on the clock information. These CPUs are connected each other through a communication device so as to timer-control the equipment.
FIG. 3 shows an example of the above mentioned system. Reference numeral 1 represents a CPU for system controlling and 2 represents a CPU for a timer. The CPU 1 for system controlling and the CPU 2 for a timer have communication interface circuits 14 and 21, respectively, which transfer a baseband data. These communication interface circuits 14 and 21 are connected through a line 4 so that one-to-one data transfer is available.
The CPU 1 for system controlling controls the operation of the equipment by a data generating circuit 13 connected to the communication interface circuit 14. In other words, the data generating circuit 13 generates a servo data based on a feedback signal supplied from a controlled part 3 containing a channel selecting circuit, a servo circuit or the like. Also, the data generating circuit 13 detects the condition of the controlled part 3, such as the amount of remaining tape and whether a cassette is fitted or not and generates a displaying data for displaying the condition. The above mentioned displaying data is transferred to the line 4 through the communication interface circuit 14 and received by a communication interface circuit 21 of the CPU 2 for a timer. The CPU 1 for system controlling contains a reference oscillator 12 connected with a crystal vibrator 11x and capacitance 11c, 11c' on its outside and the reference oscillator 12 generates a high frequency clock such as 10 MHz. The clock is divided into several lower frequencies by a frequency divider 15 and used as an operation clock (A) of the CPU 1. On the other hand, the clock is divided into about one hundredth by a frequency divider 16 and used as a communication clock (B). Further, the communication clock (B) is divided by a frequency divider 17 and used as a clock (C) which determines the transferring period of the above mentioned data. From the data generating circuit 13, the data is synchronized with the communication clock (B) and read out as a bit unit and transferred from the communication interface circuit 14 to the same circuit 21 as an unified data by a period T of the clock (C).
The CPU 2 for a timer is connected to a displaying circuit 5 for displaying an operating condition of the controlled part 3 and time, and an outer input circuit 6 composed of a remote control transmitter, a keyboard or the like. The CPU 2 processes an input data supplied from an outer input circuit 6 and at the same time processes a displaying data supplied from the CPU 1 for system controlling through the communication interface circuit 21 by using the data generating circuit 22. A data generating circuit 22 generates a data which sets up an operating condition of the equipment, such as a data for recording and stopping, based on the input data from the outer input circuit 6, and generates a program data which carries out a timer operation. The data for setting up an operation is transferred to the communication interface circuit 21 and sent to the CPU 1 for system controlling, and the program data is temporally stored in a memory of a timer controlling circuit 26. The program data consi
REFERENCES:
patent: 4821032 (1989-04-01), Shimada et al.
patent: 4847756 (1989-07-01), Ito et al.
patent: 4905212 (1990-02-01), Wakahara
Kabushiki Kaisha Toshiba
Shaw Dale M.
Smith Diane E.
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