Method for parallel instruction execution in a computer

Details Method for parallel instruction execution in a computer Method for parallel instruction execution in a computer

1990-02-14

1993-08-31

Lall, Parshotam S.

Boots, shoes, and leggings

3642318, 3642598, 3642599, 3642624, 364DIG1, G06F 922, G06F 930

Patent

active

052416364

ABSTRACT:
A method for parallel instruction execution in a computer is described. If the computer is executing in the single-instruction mode and the computer encounters a first type of instruction with a dual-instruction mode bit having a first value, then one more single instruction is executed before dual-instruction mode instruction execution begins. The first type of instruction is an instruction having a dual-instruction mode bit. The dual-instruction mode instruction execution occurs in parallel. If the computer is executing in the dual-instruction mode and the computer encounters the first type of instruction with the dual-instruction mode bit having a second value, wherein the second value is different from the first value, then one more dual instruction is executed before single-instruction mode instruction execution resumes.

REFERENCES:
patent: 4631663 (1986-12-01), Chilinski et al.
patent: 4891787 (1990-01-01), Gifford
patent: 5067069 (1991-11-01), Fite et al.

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