Instruction preprocessor for conditionally combining short memor

Details Instruction preprocessor for conditionally combining short memor Instruction preprocessor for conditionally combining short memor

1990-08-29

1992-11-10

Fleming, Michael R.

Boots, shoes, and leggings

3642287, 3642541, 3642476, 364DIG1, 3642624, G06F 930, G06F 938

Patent

active

051631393

ABSTRACT:
An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction preprocessing unit, coupled to the internal instruction memory, combines the two sequentially adjacent instructions into a single long instruction word when the two instructions meet predefined criteria for being combined. The first of the two instructions is combined with a no-operation instruction to generate a long instruction word when the predefined criteria are not met. In that case, the second instruction [may be accessed again] is used during the next instruction fetch cycle as the first of the two sequentially adjacent instructions to be processed during that next instruction fetch cycle.

REFERENCES:
patent: 3611306 (1971-10-01), Reigel et al.
patent: 3689895 (1972-09-01), Kitamura
patent: 3766527 (1973-10-01), Briley
patent: 3771141 (1973-11-01), Culler
patent: 3775756 (1973-11-01), Balser
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4471426 (1984-09-01), McDonough
patent: 4594655 (1986-06-01), Hao et al.
patent: 4594659 (1986-06-01), Guenthner et al.
patent: 4752873 (1988-06-01), Shonai et al.
patent: 4777594 (1988-10-01), Jones et al.
patent: 4794517 (1988-12-01), Jones et al.
patent: 4831515 (1989-05-01), Kamada et al.
patent: 4837678 (1989-06-01), Culler et al.
patent: 4916652 (1990-04-01), Schwarz et al.
patent: 4942525 (1990-07-01), Shintani et al.
patent: 4943915 (1990-07-01), Wilhelm et al.
patent: 4945511 (1990-07-01), Itomitsu et al.
patent: 4949250 (1990-08-01), Bhandarkar et al.
patent: 4953078 (1990-08-01), Petit
patent: 4956770 (1990-09-01), Johnson et al.
patent: 4967339 (1990-10-01), Fukumaru et al.
"Supercomputer Expands Parallel Processing Operations", Computer Design, Aug. 15, 1985, pp. 76-81.
"Eliminating the Overhead of Floating Point Load and Store Instructions by Decoding Two Instructions per Cycle in the Floating Point Unit", T. K. M. Agerwala et al., IBM TDB, vol. 25, No. L, Jun. 1982, pp. 126-129.

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