Phase locked loop reference slaving circuit

Details Phase locked loop reference slaving circuit Phase locked loop reference slaving circuit

1991-10-03

1993-08-31

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 17, 331 27, 331DIG2, H03L 7093, H03L 7095

Patent

active

052412857

ABSTRACT:
A phase locked loop circuit may be utilized as a low jitter clock regenerator in order to generate an extremely stable low jitter signal which is to a large extent immune from input phase and frequency noise. The slaving clock generates an output at a fixed phase relationship to a reference input. The clock regenerator is advantageously implemented by a logic gate type phase detector connected to a multi-stage loop filter. The loop filter output is connected to a phase correction circuit whose output is mixed with the loop filter output to provide a control input to a voltage controlled oscillator. The voltage controlled oscillator output may be provided directly, or through a frequency divider, to a feed-back input of the phase detector.

REFERENCES:
patent: 3993958 (1976-11-01), Cutsogeorge
patent: 4118674 (1978-10-01), Ball
patent: 4774480 (1988-09-01), Sato et al.
patent: 4855683 (1989-08-01), Troudet et al.
patent: 4862485 (1989-08-01), Guinea et al.
patent: 4928075 (1990-05-01), Leis
patent: 4937537 (1990-06-01), Nyqvist
patent: 5036216 (1991-07-01), Hohmann et al.
patent: 5036294 (1991-07-01), McCaslin

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