Direct memory access (DMA) controller utilizing a delayed column

Details Direct memory access (DMA) controller utilizing a delayed column Direct memory access (DMA) controller utilizing a delayed column

1996-04-01

1998-03-24

Barry, Lance Leonard

Boots, shoes, and leggings

36424231, G06F 1312

Patent

active

057322848

ABSTRACT:
Address generators output addresses of transfer data of transfer origin and destination DRAM's. Updating of the transfer addresses from the address generators during execution of DMA is performed based on a CAS signal from a timing signal generator. A delay element delays the CAS signal by a time which is the sum of an access time of the transfer origin DRAM and a data set-up time of the transfer destination DRAM. A transfer data counter counts the number of leading edges of the CAS signal while a RAS signal from the timing signal generator is held active. When a counted value reaches a preset value, the transfer data counter outputs continuous data transfer suspension information to the timing signal generator. With this arrangement, the halt in operation of a CPU due to continuous occupation of a bus is effectively prevented while achieving the increased data transfer rate.

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Patent Abstracts of Japan, vol. 95, No. 10, JP-A-07 281992, Oct. (1995).
"Digital RAS/CAS Generation for Dynamic Memories", IBM Technical Bulletin, vol. 31, No. 12, May (1989), pp. 28-30.
"Dynamic Random Access Memory Refresh Method in Triple-Modular-Redundant System", IBM Technical Bulletin, vol. 36, No. 7, Jul. (1993), pp. 7-12.

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