Pipeline system branch history table storing branch instruction

Details Pipeline system branch history table storing branch instruction Pipeline system branch history table storing branch instruction

1997-01-14

1998-03-24

Harrell, Robert B.

G06F 949

Patent

active

057322546

ABSTRACT:
In an information processing apparatus, an instruction read inhibit bit is provided for branch instruction address and target instruction address registered in pair in the branch history. When the reading of a target instruction predicted from the pair of addresses is inhibited, the instruction read inhibit bit is set to an ON state. When execution of the predicted target instruction is canceled due to the difference between the predicted target instruction and an actual target instruction and the actual target instruction is read again, an instruction read inhibit bit setting section sets the instruction read inhibit bit of the pair of addresses in the branch history to the ON state. Accordingly, even when the information processing apparatus is of a pipeline processing type and the address of the target instruction is changed every time the identical branch instruction appears, it becomes possible to execute the branch instruction without wasting time and to effectively utilize the branch history, thereby increasing the processing speed of the branch instruction, i.e., improving the information processing performance.

REFERENCES:
patent: 4334268 (1982-06-01), Boney et al.
patent: 5394529 (1995-02-01), Brown, III et al.
patent: 5404467 (1995-04-01), Saba et al.
patent: 5519841 (1996-05-01), Sager et al.
patent: 5564118 (1996-10-01), Steely, Jr. et al.

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