Multi-function microprocessor wait state mechanism using externa

Details Multi-function microprocessor wait state mechanism using externa Multi-function microprocessor wait state mechanism using externa

1997-01-20

1998-03-24

Harvey, Jack B.

395551, 395560, 395880, G06F 112

Patent

active

057322503

ABSTRACT:
A wait state mechanism for lengthening a microprocessor's bus cycle to allow data transfers between slower off-chip devices. A microprocessor is responsive to a bus control signal generated by external programmable logic which instructs the microprocessor to insert wait states of varying number depending on the component involved in a bus transaction. The microprocessor receives only a single input from the programmable logic and varies its bus cycle length accordingly.

REFERENCES:
patent: 4691289 (1987-09-01), Thaden et al.
patent: 5239639 (1993-08-01), Fischer et al.
patent: 5438614 (1995-08-01), Rozman et al.
patent: 5586275 (1996-12-01), Ehlig et al.

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