Multi-memory access limiting circuit for a multi-memory device

Details Multi-memory access limiting circuit for a multi-memory device Multi-memory access limiting circuit for a multi-memory device

Filed on

1996-04-12

Date issued

1998-03-24

Examiner

Chan, Eddie P.

Other Related Categories

395186, G06F 1216

Type

Patent

Status

active

Patent number

057322457

Description

ABSTRACT:
The memory access limiting circuit detects when two or more of memory units associated with a microprocessor control system have been accessed enabled concurrently representing an error condition. The memory access limiting circuit is part of an integrated circuit. The integrated circuit also includes an address decoding for receiving the unique address signal and causing a write enable signal to be generated for the memory units and one of a plurality chip select signals to be generated for a respective one of the memory units. The monitoring circuit monitors the pin levels of the integrated circuit assigned for enabling the respective memory unit. The monitoring circuit generates a first output signal when a respective one of the memory unit chip select signals has been enabled and a second output signal when a plurality of chip select signals have been enabled. The second output signal is directed to the microprocessor for corrective action.

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patent: 5179540 (1993-01-01), Stockton
patent: 5276844 (1994-01-01), Aebi et al.
patent: 5303181 (1994-04-01), Stockton

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