Method of manufacturing semiconductor device having interconnect

Details Method of manufacturing semiconductor device having interconnect Method of manufacturing semiconductor device having interconnect

1992-08-06

1993-08-31

Thomas, Tom

Fishing, trapping, and vermin destroying

437 44, 437 47, 437 48, 437 60, 437919, H01L 2170

Patent

active

052408728

ABSTRACT:
A semiconductor device includes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

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Kimura et al, "A New Stacked Capacitor DRAM Cell . . . ", IEEE International Electron Devices Meeting, 1988 pp. 596-599.
"Novel Stacked Capacitor Cell for 64 Mb DRAM", Wakamiya, et al., VLSI Technology Symposium, 1989, pp. 69-70.

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