Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1997-02-14
1998-03-24
Le, Vu A.
Static information storage and retrieval
Addressing
Plural blocks or banks
36523008, 36518901, G11C 800
Patent
active
057320403
ABSTRACT:
A memory cell array is divided into m.times.n blocks, m columns of blocks in the direction of row and n rows of blocks in the direction of column, each block having dynamic memory cells arranged in a matrix. Sense amplifier circuits are provided so as to correspond to the blocks and amplify the data read from the selected memory cell or the data to be written into the selected memory cell. Data buses are provided so as to correspond to the blocks and are connected to the sense amplifier circuits via column select gates. A row decode circuit decodes a row address signal and selects a row of memory cells in the memory cell array. A column decode circuit decodes a column address signal and specifies a column of memory cells in the memory cell array. Those of the blocks arranged in the same row in the memory cell array share the row decode circuit and said data buses. Those of the blocks arranged in the same column in the memory cell array share the column decode circuit. An n number of blocks arranged in a column of the blocks are selectively activated simultaneously, and the data in the memory cells in the column selected by the column decode circuit is read and written in parallel via the individual data buses for the activated blocks.
REFERENCES:
patent: 5274596 (1993-12-01), Watanabe
patent: 5274597 (1993-12-01), Ohbayashi et al.
patent: 5528552 (1996-06-01), Kamisaki
IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995; "A. 1.6 Gbyte/s Data Transfer Rate * Mb Embedded DRAM", Shinji Miyano, et al.
1993 IEEE International Solid-State Circuits Conference, Session 3, Non-Volatile, Dynamic, and Experimental Memories, Paper WP 3.5: "A 30ns 256Mb DRAM with Multi-Divided Array Structure", Tadahiko Sugibayashi, et al.
Kabushiki Kaisha Toshiba
Le Vu A.
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