Low-power high performance adder

Details Low-power high performance adder Low-power high performance adder

1995-12-04

1998-03-24

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

057320080

ABSTRACT:
A low power high performance adder using a conditional sum adder (CSA) architecture and complementary pass logic (CPL) implementation. The adder comprises a plurality of blocks, each block including a conditional sum cell and an output multiplexer. Each block except the first, also comprises a block of 2:1 multiplexers intermediate the conditional sum cell and the output multiplexer. The adder according to the present invention operates with lower power consumption and at greater speed than prior art adder architectures.

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