Semiconductor device MOS gated

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With extended latchup current level

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Details

257329, 257341, 257342, H01L 2974, H01L 31111

Patent

active

057316040

ABSTRACT:
A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask to sequentially form a cell body and a source region within the cell body, and a second mask step to form, by a silicon etch, a central opening in the silicon surface at each cell and to subsequently undercut the oxide surrounding the central opening. A contact layer then fills the openings of each cell to connect together the body and source regions. Only one critical mask alignment step is used in the process.

REFERENCES:
patent: 4598461 (1986-07-01), Love
patent: 4920064 (1990-04-01), Whight
patent: 5008725 (1991-04-01), Lidow et al.
patent: 5079602 (1992-01-01), Harada
patent: 5223732 (1993-06-01), Clark
patent: 5302537 (1994-04-01), Strack
patent: 5304837 (1994-04-01), Hierold

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