Scannable latch for multiplexor control

Details Scannable latch for multiplexor control Scannable latch for multiplexor control

1994-09-16

1996-06-18

Canney, Vincent P.

Excavating

371 27, G06F 1100

Patent

active

055286011

ABSTRACT:
An improved test circuit and method for integrated circuits are disclosed. The test circuit uses a level sensitive scan design for use with a multiplexor having a plurality of pass gates. The test circuit includes a plurality of latches, each having a functional input, a scan input and an output. The outputs are coupled to the multiplexor pass gates. A first set of mutually exclusive, or orthogonal, signals is placed on the functional inputs of the latches for selecting one of the pass gates. A signal encoder is used to form a reduced set of signals, based on the first set of signals. The reduced set of signals is further modified by a modifying means, such as a shift register. The modified signal is then decoded by a decoding means for generating the next set of orthogonal signals placed on the scan inputs. Also, an output signal is then transmitted as an evaluation signal to confirm the accuracy of the integrated circuit.

REFERENCES:
patent: 4581739 (1986-04-01), McMahon, Jr.
patent: 4602210 (1986-07-01), Fasang et al.
patent: 4780874 (1988-10-01), Lenoski et al.
patent: 4870345 (1989-09-01), Tomioka et al.
patent: 4980889 (1990-12-01), DeGuise et al.
patent: 5252917 (1993-10-01), Kadowaki
patent: 5410551 (1995-04-01), Edwards et al.

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