Patent
1997-05-07
1999-07-13
Beausoliel, Jr., Robert W.
G06F 1100
Patent
active
059238305
ABSTRACT:
A non-intrusive power control for a fault tolerant computer system which uses redundant voting at the hardware clock level. The computer includes three or more commercial central processing units (CPUs) operating synchronously. Outputs to system memory and system bus are voted by a radiation tolerant gate array which may be implemented in a custom integrated circuit. An interface control coupled to the voter can remove or connect power from a CPU and adjust CPU inputs, preventing damage to the components without terminating an operating program. The inputs and outputs at each write to and read from system memory are voted at each CPU clock cycle. A vote status and control circuit "reads" the status of the vote and controls the state of the CPUs using hardware and software. The system logic selects the best chance of recovering from a detected fault by re-synchronizing all CPUs, powering down a faulty CPU, or switching to a spare computer, resetting and re-booting the substituted CPU.
REFERENCES:
patent: 4015246 (1977-03-01), Hopkins, Jr. et al.
patent: 4799140 (1989-01-01), Dietz et al.
patent: 4926281 (1990-05-01), Murphy
patent: 4967347 (1990-10-01), Smith et al.
patent: 5276823 (1994-01-01), Cutts, Jr. et al.
patent: 5423024 (1995-06-01), Cheung
patent: 5572620 (1996-11-01), Reilly et al.
patent: 5596756 (1997-01-01), O'Brien
patent: 5666483 (1997-09-01), McClary
patent: 5799198 (1998-08-01), Fung
Johnson, Design and Analysis of Fault-Tolerant Digital Systems, Addison-Wesley Publishing Company, pp. 324-329, Dec. 1989.
Butler et al., "Techniques for Modeling the Reliability of Fault-Tolerant System with Markov State-Space Approach", NASA Reference Pub. 1348, Sep. 1995.
Nelson, Victor P. et al., Fault-Tolerant Computing (A Tutorial), no date.
Mathur, Francis P. et al., "Reliability Modeling and Analysis of General Modular Redundant Systems", published in IEEE Transaction Reliability, vol. R-24, No. 5, Dec. 1975.
Larson, Robert E., "Reconfigurable Distributed Computer System for On-Board Satellite Applications", published by Expert Base Systems, Inc. and submitted to DARPA, Apr. 30, 1987.
Barillot, Catherine et al., Review of Commercial Spacecraft Anomalies and Single-Event-Effect Occurrences, published in IEEE Transactions on Nuclear Science, vol. 4, Apr. 2, 1996, pp. 453-460.
Akers, L.D., "Microprocessor Technology and Single Event Upset Susceptibility", published in Small Satellites, 1996, pp. 1-10.
Krishna, C.M. et al., "Synchronization and Fault-Masking in Redundant Real-Time Systems", published in IEEE, 1984, pp. 152-157.
Maurer, Richard H. et al., "Single Event Upset and Latchup Sensitive Devices in Satellite Systems", published by the Johns Hopkins University Applied Physics Laboratory, no date.
McClusky, E.J., "Hardware Fault Tolerance", published by Center for Reliable Computing, Stanford University, 1986.
Schmid, H. et al., "Critical Issues in the Design of a Reconfigurable Control Computer", published in IEEE, 1984, pp. 36-41.
Pradhan, Dhiraj K., "Fault Tolerant Multiprocessor Link and Bus Network Architectures", published in IEEE Transactions on Computers, Nol. 34, No. 1, Jan. 1985, pp. 33-45.
Siewiorek, Daniel P. et al., "Reliable Computer Systems", Second Edition, published by Digital Press, 1992.
"Single Event Effect Criticality Analysis", pubication sponsored by NASA Headquarters, Feb. 15, 1996.
Fuchs Stephen
Wardrop Andrew J.
Beausoliel, Jr. Robert W.
Elmore Stephen C.
General Dynamics Information Systems, Inc.
Kubida William J.
Langley Stuart T.
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