Clock wiring design method for integrated circuit

Details Clock wiring design method for integrated circuit Clock wiring design method for integrated circuit

1996-11-21

1999-07-13

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, G06F 1750

Patent

active

059235705

ABSTRACT:
In a gate array type automatic wiring design, after arranging macrocells necessary for forming an integrated circuit, the wiring operation for clock wires 16, 18a to 18c is performed for macrocells A.sub.1, A.sub.2, B.sub.1 to B.sub.3, C.sub.1, C.sub.2 that are sequence circuits such as flip-flop circuits. After wiring parameters such as clock wire width and route as well as clock buffer connecting position have been determined based on these wiring data of the clock wires, the re-wiring operation for the clock wires 16, 18a to 18c and the arranging operation for a clock driver 12 and clock buffers 14, 20a to 20c are performed. The macrocell re-arranging operation and the wiring operation between the macrocells are thereafter performed. Such wiring design is applicable to standard cell type automatic wiring systems.

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Chung et al. ("Optimal buffered clock tree synthesis", IEEE, Proceedings of the Seventh Annual IEEE International ASIC Conference and Exhibit, Sep. 19, 1993, pp. 130-133).
Menezes et al. ("Skew reduction in clock trees using wire width optimization", IEEE, Proceedings of IEEE Custom Integrated Circuits Conference -CICC '93, May 9, 1993, pp. 9.6.1-4).
Pullela et al. ("Skew and Delay Optimization For Reliable Buffered Clock Trees", IEEE Comput. Soc. Press, Proceedings of 1993 International Conference on Computer Aided Design, Nov. 7, 1993, pp. 556-562).

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