Bus driver/latch with second stage stack input

Details Bus driver/latch with second stage stack input Bus driver/latch with second stage stack input

1978-09-25

1980-08-05

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307203, 307238, 307279, H03K 3281, H03K 3353

Patent

active

042163897

ABSTRACT:
A latching circuit is disclosed having series connected first and second stage MOSFET devices within a first inverter circuit. An output signal provided at the upper node of the series connected devices is coupled by a feedback MOSFET to the input of a second MOSFET inverter. The output of the second MOSFET inverter is coupled to the gate of the first series connected MOSFET device while the input signal to be latched is coupled to the gate of the second of the series connected MOSFET devices. The lower output node of the series connected MOSFET devices is used to provide an output signal to a data bus so that the logic state stored by the latching circuit can be accessed. The latching circuit is controlled by timing signals such that the output signal provided by the lower node is in the proper logic state whenever the latching circuit is to be coupled to the data bus.

REFERENCES:
patent: 3725792 (1973-04-01), Kellogg
patent: 3895240 (1975-07-01), Kawagoe
patent: 3904888 (1975-09-01), Griffin et al.
patent: 3959781 (1976-05-01), Mehta et al.
patent: 4063117 (1977-12-01), Langesen
patent: 4146802 (1979-03-01), Moench
McDonald, "Multivibrator"; IBM Tech. Discl. Bull.; vol. 16, No. 8, pp. 2515; 1/1974.
Anderson, "Address Encoding Circuit"; IBM Tech. Discl. Bull.; vol. 17, No. 3, pp. 796-797; 8/1974.

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