Integrated circuit package and manufacturing method

Details Integrated circuit package and manufacturing method Integrated circuit package and manufacturing method

1979-07-27

1980-12-02

McQuade, John

Geometrical instruments

29848, 156630, 174 52FP, H05K 111

Patent

active

042367778

ABSTRACT:
An integrated circuit package for establishing electrical contact with the terminal areas or pads of an integrated circuit chip comprises an insulating substrate having a flat surface in which there are embedded a plurality of electrodeposited conductors. The conductors have inner ends in a chip-receiving zone of the flat surface and have outer end portions which are remote from the chip-receiving zone. The inner ends of the conductors have contact bumps or promontories extending above the flat surface and located such that when a chip is placed on the promontories, they will be against the terminal areas of the chip. The chip can be held against the promontories by a suitable clamping means and contact established with the conductors at their outer ends by suitable connecting means. The device is particularly useful for testing chips prior to their being placed in service. The integrated circuit package is produced by etching depressions in a copper foil, electrodepositing conductors in the depressions and on the surface of the foil while controlling the locations of the conductors by suitable masking, molding the substrate against the foil so that the conductors are embedded in the substrate, and then etching away the copper foil.

REFERENCES:
patent: 2692190 (1954-10-01), Pritkin
patent: 3013188 (1961-12-01), Kohler
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patent: 3691289 (1972-09-01), Rohloff
patent: 3963315 (1976-06-01), Bonis
patent: 3972062 (1976-07-01), Hopp
patent: 4035046 (1977-07-01), Kloth

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