Method of controlling parallel processing at an instruction leve

Details Method of controlling parallel processing at an instruction leve Method of controlling parallel processing at an instruction leve

1996-02-05

1999-04-13

Donaghue, Larry D.

395392, G06F 928

Patent

active

058945822

ABSTRACT:
Apparatus for realizing instruction level parallel processing includes an instruction buffer for storing instructions fetched from a memory until the instructions are sent from the instruction buffer, an instruction register unit for storing and issuing the sent instructions to a plurality of execution units in the order of instruction, and a judgement part for judging whether it is possible to execute a set of unissued instructions to be next issued, in parallel, as stored in the instruction buffer and/or the instruction register unit and for controlling parallel processing of the set of instructions, based on the result of a judgement on the possibility of parallel processing.

REFERENCES:
patent: 5233694 (1993-08-01), Hotta et al.
patent: 5442760 (1995-08-01), Rustad et al.
patent: 5613080 (1997-03-01), Ray et al.
Pleskun et al. The Performance Potential of Multiple Functional Unit Processors IEEE, 1988.

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