Multiplexer for use in a full adder having different gate delays

Details Multiplexer for use in a full adder having different gate delays Multiplexer for use in a full adder having different gate delays

1991-10-23

1993-08-03

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307472, 307246, 307594, 364784, H03K 17693

Patent

active

052332330

ABSTRACT:
The semiconductor integrated circuit device includes a select gate for selectively transmitting a signal. The select gate includes a first gate for receiving and transferring a first logic signal to an output node, and a second gate for receiving and transferring a second logic signal to the output node. The first and second gates turn on complementarily to each other. The first gate has an output load capacitance viewed from the output node less than that of the second gate. The first gate receives, as the first logic signal, a signal not required to be transmitted at a high speed, or a signal of a predetermined logic level or a fixed level. The second gate receives, as the second signal, a signal to be transmitted at a high speed. Since the second gate has a less output load capacitance, the second gate is allowed to transmit a signal at a high speed.

REFERENCES:
patent: 4031379 (1977-06-01), Schwartz
patent: 4371797 (1983-02-01), Frank
patent: 4541067 (1985-09-01), Whitaker
patent: 4730266 (1988-03-01), van Meerbergen et al.
patent: 4940908 (1990-07-01), Tran
patent: 4988902 (1991-01-01), Dingwall
"Principles of CMOS VLSI Design", Neil H. E. Weste et al., pp. 202-203, 1985.

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