System and method for implementing fast high addressability erro

Details System and method for implementing fast high addressability erro System and method for implementing fast high addressability erro

1994-08-03

1996-06-18

Coles, Sr., Edward L.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358448, 358455, 358456, 358465, H04N 140

Patent

active

055283845

ABSTRACT:
A method and system implements a high addressability characteristic into an error diffusion process. A grey level value representing a pixel is received. The grey level value is interpolated to generate subpixel grey level values which correspond to a second resolution. A threshold circuit thresholds the interpolated grey level value. In parallel to the interpolation circuit and threshold circuit is an error circuit which generates a plurality of possible error values. One of the plurality of possible error values is selected based on the number of subpixels exceeding a threshold value. A portion of the selected error value is then diffused to adjacent pixels on a next scanline.

REFERENCES:
patent: 5121447 (1992-06-01), Tanioka et al.
patent: 5271070 (1993-12-01), Truoung et al.

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