1989-02-21
1990-06-19
James, Andrew J.
357 43, 357 47, H01L 2712
Patent
active
049358006
ABSTRACT:
This invention discloses a semiconductor integrated circuit in which an analog circuit and a digital circuit are formed on a single chip. The semiconductor integrated circuit includes a p-type semiconductor region, an n.sup.+ -type buried region formed on the p-type semiconductor region, an n-type semiconductor region formed on the n.sup.+ -type buried region, a first isolation portion, extending through the n-type semiconductor region and the n.sup.+ -type buried region and reaching the p-type semiconductor region, for isolating adjacent transistors in an analog circuit formed on the n-type semiconductor region, and a second isolation portion, formed in the n-type semiconductor region, for isolating adjacent transistors in the n-type semiconductor region.
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Patent Abstracts of Japan, vol. 9, No. 189 (E-33) [1912], Aug. 6, 1985; & JP-A-60 57 950 (Hitachi Seisakusho K. K.) 03-04-1985.
M. Suzuki et al., "A 165 ps/Gate 5000-Gate ECL Gate Array," Japanese Journal of Applied Physics, Supplements 17th Conference on Solid State Devices and Materials, 25th-27th, Aug. 1985, pp. 377-380.
James Andrew J.
Kabushiki Kaisha Toshiba
Prenty Mark
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