Semiconductor memory device with improved stacked capacitor stru

Details Semiconductor memory device with improved stacked capacitor stru Semiconductor memory device with improved stacked capacitor stru

1989-07-07

1992-03-31

James, Andrew J.

357 41, 357 51, 357 55, 357 59, H01L 2968, H01L 2702, H01L 2906, H01L 2904

Patent

active

051012510

ABSTRACT:
A DRAM having stacked capacitor cell comprises one transfer gate transistor and one capacitor. A thick insulating film having flat surface is formed on the surface of the transfer gate transistor and the like. A conductive film is formed on a surface of one impurity region of the transfer gate transistor. An opening portion deep enough to reach the conductive film is formed in the insulating film. The capacitor is formed in the opening portion and on the upper surface of the insulating film. A lower electrode of the capacitor is connected to the conductive film. An insulating film having a flat surface is formed by a reflow process employing thermal processing, plasma ECR CVD method and the like.

REFERENCES:
patent: 4151607 (1979-04-01), Koyanagi et al.
patent: 4641166 (1987-02-01), Takemae et al.
patent: 4794563 (1988-12-01), Maeda
patent: 4894696 (1990-01-01), Takeda et al.
patent: 4907046 (1990-03-01), Ohji et al.
Takashi Akahori, "Planarization of Insulating Interlayer by Bias ECR Plasma CVD" Semi Technology Symposium (Nov. 28, 1988), pp. 127-137.
M. Kumanoya et al., "A 90ns 1Mb DRAM with Multi-Bit Test Mode," IEEE International Solid-States Circuits Conference (1985), pp. 240-241.

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