Non-restoring fixed-point divider apparatus

Details Non-restoring fixed-point divider apparatus Non-restoring fixed-point divider apparatus

1996-11-15

1997-09-30

Ngo, Chuong D.

Boots, shoes, and leggings

G06F 752

Patent

active

056732155

ABSTRACT:
A divider for use in a data processing system and method of operation is disclosed The divider apparatus includes three 67-bit adders, coupled in parallel with one another for performing add or subtract functions, each adder being precharged during a first clock phase and executing selected functions during a second clock phase, which both occur during a single clock cycle. The first adder is connected to a first and second multiplexor, for selecting respective first and second operands. A third multiplexor, coupled to the second adder, is used to select a first operand for the second adder. Fourth and fifth multiplexors, which are coupled to the third adder, are used to select a respective first and second operand for the third adder. An adder operand select logic is coupled to the adders and the multiplexors for selecting whether to perform the add or subtract functions and for selecting which operands the multiplexors are to feed to their respective adders. An operand selection circuit is further added, which is coupled to the multiplexors and the adder operand select logic. The divider apparatus further comprising a remain quotient determination circuit coupled to the adders, and used for determining when a divide operation has been completed, what the divide result is, and whether there is a remainder quotient.

REFERENCES:
patent: 5105378 (1992-04-01), Mori
patent: 5339267 (1994-08-01), Ito
patent: 5420809 (1995-05-01), Read et al.

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