Method of making stacked surrounding reintrant wall capacitor

Details Method of making stacked surrounding reintrant wall capacitor Method of making stacked surrounding reintrant wall capacitor

1990-11-16

1992-03-31

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437228, 437235, 437919, H01L 2170

Patent

active

051008254

ABSTRACT:
A stacked surrounding reintrant wall capacitor (SSRWC) using a modified stacked capacitor storage cell fabrication process. The SSRWC is made up of polysilicon structure, having an elongated v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal stacked capacitor cell.

REFERENCES:
patent: 4742018 (1988-03-01), Kimura et al.
"3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS", IEDM, Dig. Tech., Papers, pp. 592-595, 1988 by T. Ema, S. Kawanago, T. Nishi, S. Yoshida, H. Nishibe, T. Yabu, Y. Kodama, T. Nakano and M. Taguchi.
"A Spread Stacked Capacitor (SCC) Cell for 64 Mbit DRAMS", IEDM, Dig. Tech. Papers, pp. 31-34, 1989, by S. Inoue, K. Hieda, A. Hitayama, F. Horiguchi and F. Masuoka.

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