Non-volatile semiconductor memory device and method of manufactu

Details Non-volatile semiconductor memory device and method of manufactu Non-volatile semiconductor memory device and method of manufactu

1991-01-04

1992-03-31

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 50, H01C 2128

Patent

active

051008181

ABSTRACT:
First, second, third and fourth impurity regions are formed on a major surface of a semiconductor substrate with prescribed spaces, to define first, second and third channel regions in portions held between the same. A select gate is formed on the first channel region through an insulating film, to define a transistor with the first and second impurity regions. A part of a control gate is formed on the third channel region through an insulating film, to define a transistor with the third and fourth impurity regions. A floating gate is formed on the second channel region and parts of the select gate and the control gate through an insulating film, to define a transistor with the second and third impurity regions. Both end portions of the floating gate are inwardly separated from upper positions of respective outer ends of parts of the select gate and the control gate, in order to improve an effect of shielding the floating gate against a fourth impurity region. Another part of the control gate is formed on the floating gate through an insulating film. The first impurity region is connected to a bit line and the fourth impurity region is connected to a source region respectively.

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Z. Weinberg "On Tunneling in Metal-Oxide Silicon Structures", Journal of Applied Physics 53(7), Jul. 1982, pp. 5052-5056.

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