Method of forming a field effect transistor on the surface of a

Details Method of forming a field effect transistor on the surface of a Method of forming a field effect transistor on the surface of a

1990-07-20

1992-03-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 44, 437190, 357 237, H01L 21265

Patent

active

051008165

ABSTRACT:
A transistor is disclosed which comprises a gate conductor 34 insulated from a channel region 55 by a gate insulator layer 38. A spacer insulator block 46 is used to accurately space a drain region 52 a predetermined distance from the gate conductor 34. A dopant source body 48 is used to form the drain region 52 such that the formation of the drain region 52 is a self-aligned process. According to the teachings of the present invention, the drain region 52 can be accurately spaced from the gate conductor 34 to reduced field enhanced leakage current during the operation of the transistor.

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patent: 4968638 (1990-11-01), Wright et al.
patent: 4988631 (1991-01-01), Ogawa
Tanaka, "Characteristics of Offset-Structure Polycrystalline-Silicon Thin-Film Transistors", IEEE, vol. 9, No. 1, 1/88.

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