Clock-synchronized C-element group for controlling data transfer

Details Clock-synchronized C-element group for controlling data transfer Clock-synchronized C-element group for controlling data transfer

1995-11-20

1998-03-03

Butler, Dennis M.

395559, G06F 104

Patent

active

057245622

ABSTRACT:
Flows of data are controlled using an externally supplied clock. A clock-synchronized C-element C1 outputs a sending signal S1 of H level to a data latch DL1 and the subsequent clock-synchronized C-element C2 and outputs an acknowledge signal A1 of H level, in synchronization with a rise of a clock signal CLK1 which is inputted to the clock-synchronized C-element C1 after the clock-synchronized C-element C1 receives a sending signal S0 of H level. Following this, the clock-synchronized C-element C1 causes the acknowledge signal A1 to fall by the next rise of the clock signal CLK1. This latches the data latch DL1. A clock signal CLK2 rises before the clock signal CLK1 falls and rises once again. In synchronization with this rise, the clock-synchronized C-element C2 performs a similar operation. As a result, the precedent clock-synchronized C-element C1 causes the sending signal S1 to fall.

REFERENCES:
patent: 4785204 (1988-11-01), Terada et al.
patent: 4907187 (1990-03-01), Terada et al.
patent: 5553276 (1996-09-01), Dean

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