Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-10-30

1998-03-03

Canney, Vincent P.

Excavating

365201, G06F 1100

Patent

active

057243662

ABSTRACT:
The drain electrode of an N type MOSFET (Q16) is connected to a power source potential (V.sub.CC) through a fuse element (F1) (route cut-off element), and the source electrode is connected to the drain electrode of an N type MOSFET (Q17), and the drain electrode of the N type MOSFET (Q16) is connected to the input of an inverter (G16), and is also connected to a resistance element (R1) connected to a grounding potential (V.sub.SS). Having this configuration, a semiconductor memory device incorporating a test mechanism is provided in order to test plural semiconductor memory devices by using a tester having a single data judging circuit.

REFERENCES:
patent: 5555212 (1996-09-01), Toshiaki et al.
patent: 5557568 (1996-09-01), Miyamoro et al.
Takashi Ohsawa, et al., "A 60ns 4Mb CMOS DRAM with Built-in Self-Test", ISSCC Digest of Technical Papers 1987, (pp. 286-287).
Hiroki Koike, et al. "A 30ns 64Mb DRAM with Built-in Self-Test and Repair Function", ISSCC Digest of Technical Papers 1992, (pp. 150-151).

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