Boots – shoes – and leggings
Patent
1996-01-25
1999-04-20
Bowler, Alyssa H.
Boots, shoes, and leggings
39580002, 395563, 36471607, 36473604, 36474801, 36474813, 36474819, G06F 938
Patent
active
058965432
ABSTRACT:
A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory includes first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. Single, dual or quad data words of 32 bits each may be accessed in each of the memory banks during each clock cycle. The multiple data words may be transferred to one or both of the first and second computation blocks.
REFERENCES:
patent: 4164787 (1979-08-01), Aranguren
patent: 4439839 (1984-03-01), Kneib et al.
patent: 4574345 (1986-03-01), Konesky
patent: 4641238 (1987-02-01), Kneib
patent: 4754394 (1988-06-01), Brantley, Jr. et al.
patent: 4800524 (1989-01-01), Roesgen
patent: 4809217 (1989-02-01), Floro et al.
patent: 4908748 (1990-03-01), Pathak et al.
patent: 5010476 (1991-04-01), Davis
patent: 5056000 (1991-10-01), Chang
patent: 5099417 (1992-03-01), Magar et al.
patent: 5151979 (1992-09-01), Poskitt
patent: 5187795 (1993-02-01), Baluforth et al.
patent: 5274789 (1993-12-01), Costa et al.
patent: 5280532 (1994-01-01), Shenoi et al.
patent: 5317572 (1994-05-01), Satoh
patent: 5325489 (1994-06-01), Mitsuhira et al.
patent: 5361370 (1994-11-01), Sprague et al.
patent: 5390304 (1995-02-01), Leach et al.
patent: 5404522 (1995-04-01), Carmon et al.
patent: 5423010 (1995-06-01), Mizukami
patent: 5438666 (1995-08-01), Craft et al.
patent: 5471607 (1995-11-01), Garde
patent: 5608885 (1997-03-01), Gupta et al.
J.E. Brewer et al, "A Monolithic Processing Subsystem", IEEE Trans. On Components, Pack. & Manuf. Tech., Part B. vol. 17, No. 3, pp. 310-316, Aug. 1994.
J.E. Brewer et al, "A Single-Chip Digital Signal Processing Subsystem", 1994 Proceedings, Sixth Annual IEEE (ICWSI), San Francisco, CA, pp. 265-272, Jan. 1994.
IBM Technical Disclosure Bulletin, vol. 33, No. 10A, Mar. 1991, New York, pp. 1-5 Distributed Process Bulletin Board.
"MVP: The dawn of a new era in digital signal processing--Introducing TM5320C8X", Texas Instruments notes, date unknown.
C.P. Feigel, "TI Introduces Four-Processor DSP Chip", Microprocessor Report, Mar. 28, 1994, pp. 22-25.
P. Papamichalis et al. "The TMS320C30 Floating-Point Digital Signal Processor", IEEE Micro. Dec. 1988, pp. 13-29.
M.L. Fuccio et al. "The DSP32C: AT&T's Second-Generation Floating-Point Digital Signal Processor", IEEE Micro. Dec. 1988, pp. 30-48.
G.R.L. Sohie et al. "A Digital Signal Processor with IEEE Floating Point Arithmetic", IEEE Micro. Dec. 1988, pp. 49-67.
"State of the Art Power PC 620 Soars", BYTE, Nov. 1994, pp. 114 and 116.
Texas Instruments, TMS320c3X, "User's Guide", Digital Signal Processing Products, 1991, pp. 5-24-5-28.
Analog Devices Inc.
Bowler Alyssa H.
Follansbee John
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