Digital signal processor system having host processor for writin

Details Digital signal processor system having host processor for writin Digital signal processor system having host processor for writin

1991-08-27

1993-08-17

Kriess, Kevin A.

Boots, shoes, and leggings

364DIG1, 3642304, 364230, 3642421, 3642715, 395200, G06F 1516, G06F 1300

Patent

active

052376672

ABSTRACT:
A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

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