Technique to manufacture a SOI wafer and its applications in int

Details Technique to manufacture a SOI wafer and its applications in int Technique to manufacture a SOI wafer and its applications in int

1993-09-15

1995-03-28

Paladugu, Ramamohan Rao

Fishing, trapping, and vermin destroying

437 84, 437 83, 437225, 437915, H01L 21265

Patent

active

054016703

ABSTRACT:
A SOI wafer is produced by employing a bonding tool set which can be repeatedly used to reduce manufacturing cost. The use of a bonding tool set enables its application in the fabrication of IC patterns on both sides of a thin semiconductor film. A new IC fabrication method called parallel process technique is developed to manufacture integrated circuits by utilizing a bonding tool set. This parallel process technique simplifies the complex IC chip fabrication in addition to the yield improvement and the reduction of cycle time.

REFERENCES:
patent: 4109846 (1978-08-01), Pennings et al.
patent: 4824489 (1989-04-01), Cogan et al.
patent: 5129827 (1992-07-01), Hoshi et al.
patent: 5152857 (1992-10-01), Ito et al.
patent: 5160560 (1992-11-01), Welkowsky et al.

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