Fishing – trapping – and vermin destroying
Patent
1992-04-29
1993-08-17
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 3, 437 5, 437203, 437234, 148DIG80, H01L 2144
Patent
active
052368718
ABSTRACT:
A process for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface of the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.
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Fossum Eric R.
Grunthaner Frank J.
Hearn Brian E.
Jones Thomas H.
Kusmiss John H.
Miller Guy M.
The United States of America as represented by the Administrator
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