Isolation process for VLSI

Details Isolation process for VLSI Isolation process for VLSI

1992-06-01

1993-08-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 72, 437 73, 437 89, 148DIG50, H01L 2120

Patent

active

052368637

ABSTRACT:
A process for forming an IC isolation trench pattern wherein the trenches have varying widths and are filled with near intrinsic single crystal silicon. Thus, the wiring that passes over the trenches has low capacitance and active circuit devices having improved high frequency performance can be fabricated into the silicon in the trenches. This increases the utilization of surface area thereby increasing active device density for VLSI applications.

REFERENCES:
patent: 4385975 (1983-05-01), Chu et al.
patent: 4509249 (1985-04-01), Goto et al.
patent: 4689656 (1987-08-01), Silvestri et al.
patent: 4728624 (1988-03-01), Silvestri et al.
patent: 4745081 (1988-05-01), Beyer et al.
patent: 4820654 (1989-04-01), Lee
patent: 4900692 (1990-02-01), Robinson
patent: 4926233 (1990-05-01), Hutter
patent: 4929996 (1990-05-01), Hutter

Affiliated with

Also associated with

Rating

Isolation process for VLSI does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Isolation process for VLSI, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Isolation process for VLSI will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2243493