Configuration data loopback in a bus bridge circuit

Details Configuration data loopback in a bus bridge circuit Configuration data loopback in a bus bridge circuit

1996-12-19

1999-04-20

Auve, Glenn A.

395306, G06F 1338

Patent

active

RE0361917

ABSTRACT:
A method and apparatus for reducing cost and complexity of devices in a bus bridge circuit by dividing address and data paths between separate devices to reduce pin count, and by looping back "bridged" configuration data to access configuration registers. The host bridge circuit "bridges" all I/O accesses received over a host bus directly to a peripheral component bus without any decoding. The CDC is both initiator and target on the peripheral component bus for I/O access cycles generated by the host bridge circuit that are targeted for a host bridge configuration register.

REFERENCES:
patent: 4864496 (1989-09-01), Triolo et el.
patent: 4958271 (1990-09-01), Yoshida et al.
patent: 4975838 (1990-12-01), Mizuno et al.
patent: 5029074 (1991-07-01), Maskas et al.
patent: 5083260 (1992-01-01), Tsuchiya

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