Boots – shoes – and leggings
Patent
1989-05-26
1992-06-02
Shaw, Gareth D.
Boots, shoes, and leggings
364DIG1, 364DIG2, 3642393, 3642604, 3649328, 3649392, G06F 500
Patent
active
051194783
ABSTRACT:
The bit streams, transporting the frames, received from lines (6) are placed in register 12 in such a way that n bits are processed in parallel during a time interval T. Parallel processor 10 counts the consecutive logical "1" bits beginning at the low order (left most) bit of the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result, it reassembles N-bit characters, with N<n, in register (16). The frame characters to be sent on lines (6) are stored into register (28), and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive logical "1's" as a function of the value of the N bit and as a function of the bits of the previous character, to store into register (32), the bits which are sent on lines (6).
REFERENCES:
patent: 4071887 (1978-01-01), Daly et al.
patent: 4543654 (1985-09-01), Jones
patent: 4882727 (1989-11-01), Williams et al.
Calvignac Jean
Feraud Jacques
Naudin Bernard
Pin Claude
Saint-Georges Eric
Cockburn Joscelyn G.
International Business Machines - Corporation
Klock Brian L.
Shaw Gareth D.
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