Parallel/series error correction circuit

Details Parallel/series error correction circuit Parallel/series error correction circuit

1981-12-02

1984-06-26

Smith, Jerry

Excavating

371 38, G06F 1100

Patent

active

044569963

ABSTRACT:
In a data processing system, the subject error correcting circuit is connected in the bridging mode to the data bus which interconnects a processor and a memory for error detection. It is presumed that the memory words obtained from the memory are relatively error-free, and the subject circuit does not delay their transmission, but simply monitors the data. If an error in the data is detected, an error signal is generated on the next processor microcycle, the processor aborts its present operation and then fetches the corrected data from the error correction circuit. If the frequency of errors increases or if a permanent error is detected, the subject error correction circuit switches to an in-line mode where it functions much as prior art error correction circuits: delaying the transmission of each memory word until the error check is complete.

REFERENCES:
patent: 4058851 (1977-11-01), Scheuneman
patent: 4319356 (1982-03-01), Kocol et al.
patent: 4340964 (1982-07-01), Sprick et al.
Katsafouros et al., "Memory With Selective Use of Error Detection and Correction Circuits," IBM Tech. Disclosure Bulletin, vol. 16, No. 7A, 12/80, pp. 2866-2867.
Wolff, "Parallel I/O Error Detection and Correction," IBM Tech. Disclosure Bulletin vol. 7, No. 10, Mar. 1965, pp. 927-928.

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