Multi-processor computer system bus architecture

Details Multi-processor computer system bus architecture Multi-processor computer system bus architecture

1991-05-20

1994-08-09

Lall, Parshotam S.

Boots, shoes, and leggings

395800, 3642283, 3642289, 3642290, 364DIG1, G06F 1516

Patent

active

053374118

ABSTRACT:
A bus structure for a real-time multiprocessor computing system connects, for example, 16 processors, each having only two bus interfaces, without degrading processor performance or requiring partitioning by application programmers. The processors are divided into groups with each combination of two groups connected together and to memory and peripheral units via a different bus. In a computing system having first, second, third and fourth processor groups and first and second memory groups and peripheral groups, a first bus connects the first and second processor groups together and to first groups of memory and peripheral units, a second bus connects the first and fourth processors together and to second memory and peripheral groups, a third bus connects the second and third processors to the second memory and peripheral groups and a fourth bus connects the third and fourth processor groups to the first memory and peripheral groups.

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