Self-aligned gate method for making MESFET semiconductor

Details Self-aligned gate method for making MESFET semiconductor Self-aligned gate method for making MESFET semiconductor

1981-12-24

1984-06-26

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 148 15, 357 15, 357 22, 156643, H01L 21302, H01L 21265

Patent

active

044557388

ABSTRACT:
A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is self-aligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.

REFERENCES:
patent: 4209349 (1980-06-01), Ho et al.
patent: 4359816 (1982-11-01), Abbas et al.
patent: 4375643 (1983-03-01), Yeh et al.
patent: 4393578 (1983-07-01), Cady et al.
IBM Tech. Disclosure Bulletin; "Fabricating a Gate Field-Effect Transistor"; Kircher et al., vol. 13, No. 3, Aug. 1970, pp. 646-648.

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