Semiconductor memory device including arrangements to facilitate

Details Semiconductor memory device including arrangements to facilitate Semiconductor memory device including arrangements to facilitate

1992-02-18

1994-06-21

LaRoche, Eugene R.

Static information storage and retrieval

Powering

Data preservation

365222, 365227, H03K 301

Patent

active

053233549

ABSTRACT:
A multi-port memory is provided which is capable of being backed up by a battery to provide a resume function for a digital processor. In a preferred embodiment, a resume function can be provided for a VRAM without restricting the bit rate of image data or the function of the frame memory. Preferably, the memory includes a memory array MARY of memory cells of stereoscopic structure. A high voltage VCH for word line selection can be generated by a voltage-doubling word boost circuit which has its boosting ratio switched stepwise in accordance with the potential of an internal supply voltage. Moreover, a substrate potential generator is provided which has a first substrate potential generator having a relatively low current supplying capacity, which is steadily brought into an operative state, and a second substrate potential generator having a relatively high current supplying capacity which is selectively brought into an operative state. During battery backup, the multi-port memory is in a self-refresh memory. Also, the number of memory mats to be simultaneously activated in the self-refresh mode is made larger than that in the ordinary mode, and a refresh timer circuit RTM for setting the refresh period is of a diffusion layer leakage type.

REFERENCES:
patent: 4964082 (1990-10-01), Sato et al.
patent: 4984211 (1991-02-01), Tran
patent: 4985869 (1991-02-01), Miyamoto
patent: 4987559 (1991-02-01), Miyauchi et al.
patent: 5134589 (1992-07-01), Hamano
patent: 5146430 (1992-09-01), Torimaru et al.

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