Patent
1982-11-05
1985-10-08
James, Andrew J.
357 4, 357 238, 357 2314, 357 41, 357 59, 357 88, H01L 2712, H01L 2904, H01L 2978, H01L 2702
Patent
active
045463751
ABSTRACT:
A vertical IGFET comprising a substantially planar silicon wafer with a source electrode on one major surface and a drain electrode on the opposite major surface is disclosed. An insulated gate electrode, which includes a conductive finger portion surrounded by an insulating layer, is internally disposed in the silicon wafer such that a predetermined voltage applied to the gate electrode will regulate a current flow between the source and drain electrodes. The device is fabricated utilizing an epitaxial lateral overgrowth technique for depositing monocrystalline silicon over the insulated gate which is disposed on a silicon substrate.
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Blackstone Scott C.
Corboy, Jr. John F.
Jastrzebski Lubomir L.
Carroll J.
Cohen Donald S.
Glick Kenneth R.
James Andrew J.
Morris Birgit E.
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