Integrated circuit distributed geometry to reduce switching nois

Details Integrated circuit distributed geometry to reduce switching nois Integrated circuit distributed geometry to reduce switching nois

1986-08-29

1988-02-16

Edlow, Martin H.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307303, 307263, 307443, 307451, 307594, 307601, 307481, 307605, 357 231, 357 238, 357 2314, 357 42, 357 51, 357 59, H03K 17687, H03K 513, H01L 2978, H01L 2702

Patent

active

047257474

ABSTRACT:
A complimentary output pair (10) having a P-channel transistor (12) and an N-channel transistor (14) prevents output voltage spikes due to rapid changes in current with respect to time at the V.sub.cc power supply and ground (32) nodes by using a "graded turn-on." Both the P-channel transistor (12) and the N-channel (14) utilize a serpentine polysilicon gate (16), (24), in order to sequentially turn on the sub-transistors in response to a changing input. Pull-up (36) and pull-down (40) transistors are used to turn the sub-transistors (21a-j, 29a-f) off simultaneously.

REFERENCES:
patent: 4152717 (1979-05-01), Satou et al.
patent: 4462041 (1984-07-01), Glenn

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