Fishing – trapping – and vermin destroying
Patent
1992-06-22
1993-11-16
Thomas, Tom
Fishing, trapping, and vermin destroying
437238, 437240, 437964, 148DIG118, 148DIG98, 148DIG170, H01L 2102
Patent
active
052623580
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to a method of producing a silicate layer in an integrated circuit.
Silicate layers provided within integrated circuits are normally used as intermediate oxide insulation layers for electrically insulating the polysilicon plane and the diffusion areas located below the intermediate oxide insulation layer from the conductor tracks which are arranged above the intermediate oxide insulation layer and which may consist, e.g., of aluminum. Furthermore, the interradiate oxide insulation layer is used for making uniform or for rounding off topographic irregularities of the circuit structures formed on the substrate before the polysilicon structure is formed. The vertical steps of the circuit structures must be rounded off and levelled as much as possible by the intermediate oxide insulation layer, since otherwise shadowing effects may occur when the aluminum conductor tracks are produced by means of a subsequent aluminum sputtering process, and since, in addition, excessively high steps in the substrate may result in overhangs and in tearing of the aluminum conductor tracks. When the integration level of the integrated circuit increases, these problems become more and more critical, since, due to the fact that the lateral dimensions decrease as the integration level increases, the height-width ratio increases while the layer thickness of the topographic steps remains unchanged.
For the consequently necessary levelling of structured surfaces of integrated circuits, two methods are primarily used at present:
According to the first known method, a polysiloxane layer is applied by means of a spin-on process to the topologically uneven circuit structures formed on a substrate. The polysiloxane layers applied in this way are also referred to as spin-on glass (SOG). After having been applied by the spin-on process, the polysiloxane layer is converted into a silicate layer or SiO.sub.2 layer in a subsequent tempering process. In the case of this method, the chemical composition of the polysiloxane layer cannot be varied and the flow behavior and the viscosity of the polysiloxane layer as well as the layer thickness thereof can only be adjusted within close limits. When polysiloxane layers are applied by means of the spin-on process, it is technologically very difficult to produce thin layers and layers having a homogeneous thickness throughout large wafer diameters. Furthermore, it is impossible to adapt the chemical composition and, consequently, the viscosity as well as the flow properties of commercially available polysiloxanes to the requirements of a special topography of the integrated circuit, as can be necessary, for example, for filling a trench, since the adaptation of the composition and of the flow properties of the polysiloxanes can only be carried out through the manufacture thereof.
In the second known method, boron phosphorous silicate glass layers are produced in a chemical vapor deposition process (CVD) as intermediate insulation layers. This vapor deposition process uses as starting gases preferably silane compounds or organic siloxane compounds together with doping gases, such as B.sub.2 H.sub.6 and PH.sub.3, respectively, as well as oxygen (O.sub.2). These boron phosphorus silicate glass layers can be deposited by means of a purely thermal reaction at atmospheric pressure or in the low pressure range as well as in plasma. The boron phosphorus silicate glass layers have high flow temperatures and, consequently, they result in a high temperature budget in the overall production process. Furthermore, in order to prevent diffusion of boron or of phosphorus, additional diffusion-retarding cover layers, such as silicon nitride layers, have to be used, and this burdens the overall production process. Moreover, due to their complex chemical structure and composition boron phosphorus silicate glass layers are difficult to handle when subsequent process steps, such as etching of contact holes, are carried out.
The technical publication "Solid State Technology, April 1988, pages 11
REFERENCES:
patent: 4702936 (1987-10-01), Maeda et al.
patent: 4781942 (1988-11-01), Leyden et al.
patent: 5028566 (1991-07-01), Lagendijk
Baker et al.; "Photoenhanced Deposition of Silicon Oxide Thin Films Using a ovel Windowless Internal Nitrogen Discharge Lamp"; Appl. Phys. A vol. 46; pp. 243-248; 1988.
Chin et al.; "Plasma TEOS Process for Interlayer Dielectric Applications"; Solid State Technology; pp. 119-122; Apr. 1988.
Jackson et al.; "Afterglow Chemical Vapor Deposition of SiO.sub.2 "; Solid State Technology; pp. 107-111; Apr. 1988.
Levy et al.; "Low Pressure Chemical Vapor Deposition of Borophosphosilicate Glass Films Produced by Injection of Miscible DADBS-TMB-TMP Liquid Sources; J. Electrochem. Soc. Solid-State Science and Technology"; pp. 1744-1749; Jul. 1987.
Butherus et al.; "O.sub.2 Plasma-Converted Spin-On-Glass for Planarization"; J. Vac. Sci.-Technol B3(5); pp. 1352-1356; Sep./Oct. 1985.
"Radiation-Curable Polysiloxanes"; IBM Technical Disclosure Bulletin; vol. 30, No. 3, Aug. 1987.
Kulisch et al.; "Plasma-Enhanced Chemical Vapour Deposition of Silicon Dioxide Using Tetraethoxysilane as Silicon Source"; Thin Solid Films, vol. 174, No. 1, Jul. 1989, pp. 57-61.
Klumpp Armin
Sigmund Hermann
Dang Trung
Dougherty Ralph H.
Fraunhofer-Gesellschaft zur Forderung der ange-wandten Forschung
Thomas Tom
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