High frequency programmable divider

Details High frequency programmable divider High frequency programmable divider

1992-10-15

1994-08-09

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

With programmable counter

377 54, H03K 2366

Patent

active

053373391

ABSTRACT:
A high speed, synchronous, programmable frequency divider is disclosed. The divider is composed of a cascade of conventional programmable counters, each of which receives some portion of an externally supplied integer N, such that the divider produces one output pulse for every N periods of a supplied clock signal. Although conventional frequency dividers are substantially slower than the speed of their individual counters, a divider according to this invention, however, will operate at very nearly the same speed. The improved performance is achieved through (a) individually choosing the timing of the clock signal applied to each circuit of the divider, and (b) introducing a delay circuit, typically a shift register, in a feedback path. A method for determining the values of the clock timing variations and for determining an optimum number of flip-flops in the shift register is given. A divider according to the invention may be optimized either for maximum speed or for best design margins at a given speed.

REFERENCES:
patent: 5221906 (1993-06-01), Hayashi et al.
ECLinPS data manual 1990; Motorola Inc, Phoenix Ariz.
"Digital Phase Locked Loops: Theory & Design" pp. 276-281, Ulrich L. Rohde, Prentice-Hall 1983.
"The Art of Electronics", 2nd Ed., pp. 545-546; Paul Horowitz & Winfield Hill, Cambridge Press 1989.

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